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/*
	BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0.
*/

/* Standard includes. */
#include <stdlib.h>

/* Scheduler includes. */
#include "FreeRTOS.h"
#include "queue.h"
#include "task.h"

/* Demo application includes. */
#include "serial.h"
#include "type.h"
#include "target.h"
#include "uart.h"

/*-----------------------------------------------------------*/

/* Constants to setup and access the UART. */
#define serDLAB							( ( unsigned char ) 0x80 )
#define serENABLE_INTERRUPTS			( ( unsigned char ) 0x03 )
#define serNO_PARITY					( ( unsigned char ) 0x00 )
#define ser1_STOP_BIT					( ( unsigned char ) 0x00 )
#define ser8_BIT_CHARS					( ( unsigned char ) 0x03 )
#define serFIFO_ON						( ( unsigned char ) 0x01 )
#define serCLEAR_FIFO					( ( unsigned char ) 0x06 )
#define serWANTED_CLOCK_SCALING			( ( unsigned long ) 16 )

/* Constants to setup and access the VIC. */
#define serU0VIC_CHANNEL				( ( unsigned long ) 0x0006 )
#define serU0VIC_CHANNEL_BIT			( ( unsigned long ) 0x0040 )
#define serU0VIC_ENABLE					( ( unsigned long ) 0x0020 )
#define serCLEAR_VIC_INTERRUPT			( ( unsigned long ) 0 )

/* Constants to determine the ISR source. */
#define serSOURCE_THRE					( ( unsigned char ) 0x02 )
#define serSOURCE_RX_TIMEOUT			( ( unsigned char ) 0x0c )
#define serSOURCE_ERROR					( ( unsigned char ) 0x06 )
#define serSOURCE_RX					( ( unsigned char ) 0x04 )
#define serINTERRUPT_SOURCE_MASK		( ( unsigned char ) 0x0f )

/* Misc. */
#define serINVALID_QUEUE				( ( xQueueHandle ) 0 )
#define serHANDLE						( ( xComPortHandle ) 1 )
#define serNO_BLOCK						( ( portTickType ) 0 )

/************************************
*     UART value defines
************************************/
#define UART_EIGHT_BITS            0x03
#define UART_ONE_STOP              0x00
#define UART_PARITY_DISABLED       0x00
#define UART_PARITY_ENABLED        0x01
#define UART_NO_PARITY             0x00
#define UART_NO_BREAK              0x00
#define UART_PARITY_ODD            0x00
#define UART_PARITY_EVEN           0x01
#define UART_DIVISOR_ENABLE        0x80
#define UART_DIVISOR_DISABLE       0x00

#define VIC_UART0_bit  (1 << VIC_UART0)
#define VIC_UART1_bit  (1 << VIC_UART1)
typedef struct  
{
   unsigned char DLM;
   unsigned char DLL;
   unsigned char FDR;
   unsigned long int Rate;
}UartBaudStruct;

/*-----------------------------------------------------------*/

/* Queues used to hold received characters, and characters waiting to be
transmitted. */
static xQueueHandle xRxedChars;
static xQueueHandle xCharsForTx;
static volatile long lTHREEmpty = pdFALSE;

/*
const UartBaudStruct StandardBaud[7] = {
      {0, 208,  33,   2400}, // 2400     Index = 0
      {0, 104,  33,   4800}, // 4800     Index = 1
      {0, 52,   33,   9600}, // 9600     Index = 2
      {0, 26,   33,  19200}, // 19200    Index = 3
      {0, 13,   33,  38400}, // 38400    Index = 4
      {0, 8,   133,  57600}, // 57600    Index = 5
      {0, 4,   133, 115200}  // 115200   Index = 6
      }; 
*/
volatile DWORD SERIAL0Status;
volatile BYTE SERIAL0TxEmpty = 1;
volatile BYTE SERIALBuffer[BUFSIZE];
volatile DWORD SERIAL0Count = 0;
/*-----------------------------------------------------------*/

/* The ISR.  Note that this is called by a wrapper written in the file
SerialISR.s79.  See the WEB documentation for this port for further
information. */
__arm void vSerialISR( void );

/*-----------------------------------------------------------*/

xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
{
//DWORD Fdiv;
xComPortHandle xReturn = serHANDLE;
extern void ( vSerialISREntry) ( void );

	/* Create the queues used to hold Rx and Tx characters. */
	xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
	xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) );

	/* Initialise the THRE empty flag. */
	lTHREEmpty = pdTRUE;

	if(
		( xRxedChars != serINVALID_QUEUE ) &&
		( xCharsForTx != serINVALID_QUEUE ) &&
		( ulWantedBaud != ( unsigned long ) 0 )
	  )
	{
		portENTER_CRITICAL();
		{
			/* Setup the baud rate:  Calculate the divisor value. */
 
                  //Set the FIFO enable bit in the FCR register. This bit must be set for
   //proper UART operation.
     /*             
                  
   U0FCR = 1;

   //Set mode
   U0LCR_bit.WLS = UART_EIGHT_BITS;      // word length
   U0LCR_bit.SBS = UART_ONE_STOP;        // stop bitS
   U0LCR_bit.PS  = UART_PARITY_EVEN;     //Parity Type
   U0LCR_bit.PE  = UART_PARITY_ENABLED;  //Parity enabled/disabled

   U0LCR_bit.DLAB = 1;
   U0DLM = StandardBaud[4].DLM;   
   U0DLL = StandardBaud[4].DLL;  
   U0FDR = StandardBaud[4].FDR;  
   U0LCR_bit.DLAB = 0;
   U0IER_bit.RDAIE  = 1;  //Enable byte received interrupt
   U0IER_bit.THREIE = 1;  //Enable tx buf empty interrupt
   U0IER_bit.RXLSIE = 1;  //Enable line error interrupt
   U0LCR_bit.DLAB = 0;
*/
  // PINSEL4 = 0x0000000A;       /* RxD1 and TxD1 */          

           ///   PINSEL4 = 0x0000000A;       /* RxD1 and TxD1 */  
                //  deinit UART
          
        //P_INSEL4 &= ~(3 << 0);
        //P_INSEL4 &= ~(3 << 2);
                  
                  
                  
 

              
              
            
  	//PINSEL0 |= 0x40000000;	/* Enable TxD1 P0.15 */
	//PINSEL1 |= 0x00000001;	/* Enable RxD1 P0.16 */          
            
            /* RxD1 and TxD1*/
 // PINSEL4_bit.P2_0=2;
  //  PINSEL4_bit.P2_1=2;                 
        //P_INSEL4|= (2<<0);  /* RxD1 and TxD1 */
        //P_INSEL4|= (2<<2);        
  U1LCR = 0x83;    /* 8 bits, no Parity, 1 Stop bit */
  //Fdiv = ( Fpclk / 16 ) / 19200 ;  /*baud rate */

//U1DLM = Fdiv / 256;
// U1DLL = Fdiv % 256;

 
//U1FCR = 0x07;   /* Enable and reset TX and RX FIFO. */
 //U1IER = IER_RBR | IER_THRE | IER_RLS; /* Enable UART0 interrupt */       
      U1LCR = 0x03;               
   U1IER_bit.RDAIE  = 1;  //Enable byte received interrupt               
    U1IER_bit.THREIE = 1;  //Enable tx buf empty interrupt              
     U1IER_bit.RXLSIE = 1;  //Enable line error interrupt             
          U1LCR = 0x03;           
                  
     VICINTSELECT &= ~VIC_UART1_bit;                      // IRQ for this interrupt
   VICVECTADDR10 = (unsigned int)&vSerialISREntry;      // Write address of function to VIC
   
     //  VICVECTPRIORITY10 = 1;  
       
   VICINTENABLE = VIC_UART1_bit;                 
                  
                  
                  
 //*                 PINSEL0 = 0x00000050;       /* RxD0 and TxD0 */
   //  U0LCR_bit.WLS = UART_EIGHT_BITS;      // word length
  // U0LCR_bit.SBS = UART_ONE_STOP;        // stop bitS  
   
  //*  U0LCR = 0x83;    /* 8 bits, no Parity, 1 Stop bit */
  //*  Fdiv = ( Fpclk / 16 ) / 9600 ;  /*baud rate */
 //* U0DLM = Fdiv / 256;
  //* U0DLL = Fdiv % 256;
  //*    U0LCR = 0x03;   /* DLAB = 0 */
   
   // U0LCR_bit.DLAB = 0;
  //*   U0IER_bit.RDAIE  = 1;  //Enable byte received interrupt
  //*   U0IER_bit.THREIE = 1;  //Enable tx buf empty interrupt
   //*  U0IER_bit.RXLSIE = 1;  //Enable line error interrupt
  //*   U0LCR_bit.DLAB = 0;
   //*  U0LCR = 0x03;   /* DLAB = 0 */
  
 //U0LCR = 0x03;   /* DLAB = 0 */
//U0FCR = 0x07;   /* Enable and reset TX and RX FIFO. */              
                  
			/* Setup the VIC for the UART. */
    //*  VICINTSELECT &= ~VIC_UART0_bit;                      // IRQ for this interrupt
    //*  VICVECTADDR6 = (unsigned int)&vSerialISREntry;      // Write address of function to VIC
    //*  VICINTENABLE = VIC_UART0_bit;                        // Enable UART 0 interrupt.
   //U0THR = 0x31;

		}
		portEXIT_CRITICAL();

		xReturn = ( xComPortHandle ) 1;
	}
	else
	{
		xReturn = ( xComPortHandle ) 0;
	}

	return xReturn;
}
/*-----------------------------------------------------------*/

signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, portTickType xBlockTime )
{
	/* The port handle is not required as this driver only supports UART0. */
	( void ) pxPort;

	/* Get the next character from the buffer.  Return false if no characters
	are available, or arrive before xBlockTime expires. */
	if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
	{
		return pdTRUE;
	}
	else
	{
		return pdFALSE;
	}
}
/*-----------------------------------------------------------*/

void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength )
{
signed char *pxNext;

	/* NOTE: This implementation does not handle the queue being full as no
	block time is used! */

	/* The port handle is not required as this driver only supports UART0. */
	( void ) pxPort;
	( void ) usStringLength;

	/* Send each character in the string, one at a time. */
	pxNext = ( signed char * ) pcString;
	while( *pxNext )
	{
		xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );
		pxNext++;
	}
}
/*-----------------------------------------------------------*/

signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, portTickType xBlockTime )
{
signed portBASE_TYPE xReturn;

	/* The port handle is not required as this driver only supports UART0. */
	( void ) pxPort;

	portENTER_CRITICAL();
	{
		/* Is there space to write directly to the UART? */
		if( lTHREEmpty == ( long ) pdTRUE )
		{
			/* We wrote the character directly to the UART, so was
			successful. */
			lTHREEmpty = pdFALSE;
			U0THR = cOutChar;
			xReturn = pdPASS;
		}
		else
		{
			/* We cannot write directly to the UART, so queue the character.
			Block for a maximum of xBlockTime if there is no space in the
			queue.  It is ok to block within a critical section as each
			task has it's own critical section management. */
			xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime );

			/* Depending on queue sizing and task prioritisation:  While we
			were blocked waiting to post interrupts were not disabled.  It is
			possible that the serial ISR has emptied the Tx queue, in which
			case we need to start the Tx off again. */
			if( lTHREEmpty == ( long ) pdTRUE )
			{
				xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK );
				lTHREEmpty = pdFALSE;
				U0THR = cOutChar;
			}
		}
	}
	portEXIT_CRITICAL();

	return xReturn;
}

__arm void vSerial0ISR( void )
{
  BYTE IIRValue, LSRValue;
volatile BYTE Dummy;

  __enable_interrupt();   /* handles nested interrupt */

  IIRValue = U0IIR;
  IIRValue >>= 1;     /* skip pending bit in IIR */
  IIRValue &= 0x07;     /* check bit 1~3, interrupt identification */
  if ( IIRValue == IIR_RLS )    /* Receive Line Status */
  {
    LSRValue = U0LSR;
    /* Receive Line Status */
    if ( LSRValue & (LSR_OE|LSR_PE|LSR_FE|LSR_RXFE|LSR_BI) )
    {
      /* There are errors or break interrupt */
      /* Read LSR will clear the interrupt */
      SERIAL0Status = LSRValue;
      Dummy = U0RBR;    /* Dummy read on RX to clear interrupt, then bail out */
      
       U1THR = Dummy;
      
      VICADDRESS = 0; /* Acknowledge Interrupt */
      return;
    }
    if ( LSRValue & LSR_RDR ) /* Receive Data Ready */
    {
      /* If no error on RLS, normal ready, save into the data buffer. */
      /* Note: read RBR will clear the interrupt */
      SERIALBuffer[SERIAL0Count] = U0RBR;
      SERIAL0Count++;
      if ( SERIAL0Count == BUFSIZE )
      {
        SERIAL0Count = 0; /* buffer overflow */
      }
    }
  }
  else if ( IIRValue == IIR_RDA ) /* Receive Data Available */
  {
    /* Receive Data Available */
     U1THR = U0RBR;
    //UART0Buffer[UART0Count] = U0RBR;
    SERIAL0Count++;
    if ( SERIAL0Count == BUFSIZE )
    {
      SERIAL0Count = 0; /* buffer overflow */
    }
  }
  else if ( IIRValue == IIR_CTI ) /* Character timeout indicator */
  {
    /* Character Time-out indicator */
    SERIAL0Status |= 0x100; /* Bit 9 as the CTI error */
  }
  else if ( IIRValue == IIR_THRE )  /* THRE, transmit holding register empty */
  {
    /* THRE interrupt */
    LSRValue = U0LSR; /* Check status in the LSR to see if valid data in U0THR or not */
    if ( LSRValue & LSR_THRE )
    {
      SERIAL0TxEmpty = 1;
    }
    else
    {
      SERIAL0TxEmpty = 0;
    }
  }


                 VICADDRESS = 0;   // Clear all interrupts in VIC. This resets the priority hardware. 
  
}

/*-----------------------------------------------------------*/





__arm void vSerialISR( void )
{
signed char cChar;
portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;

	/* What caused the interrupt? */
	switch( U1IIR & serINTERRUPT_SOURCE_MASK )
	{
		case serSOURCE_ERROR :	/* Not handling this, but clear the interrupt. */
								//*cChar = U0LSR;
                                                                cChar = U1LSR;
                  
								break;

		case serSOURCE_THRE	:	/* The THRE is empty.  If there is another
								character in the Tx queue, send it now. */
								if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE )
								{
									//U0THR = cChar;
                                                                  
                                                                  U1THR = cChar;
								}
								else
								{
									/* There are no further characters
									queued to send so we can indicate
									that the THRE is available. */
									lTHREEmpty = pdTRUE;
								}
								break;

		case serSOURCE_RX_TIMEOUT :
		case serSOURCE_RX	:	/* A character was received.  Place it in
								the queue of received characters. */
								//cChar = U0RBR;
                                                           //    cChar = U1DLL;
                            
                                                                    //   while (U1LSR & (1<<U1LSR_RDR_BIT)){
                                                                          cChar = U1DLL;
                                                                        //  unsigned char c = U1RBR;
                                                                      ///    buffer_put(&cbuf, c);
                                                                           UART_RX_DATE(cChar);

                                                                           
                                                                      //  }
                                                              //  cChar = U1RBR;
                                                            ////    UART_RX_DATE(cChar);
                                                           //     U0THR = cChar;
                                                                
                                                                
								xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken );
								break;

		default				:	/* There is nothing to do, leave the ISR. */
								break;
	}

	/* Exit the ISR.  If a task was woken by either a character being received
	or transmitted then a context switch will occur. */
	portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );

	/* Clear the ISR in the VIC. */
                VICADDRESS = 0;   // Clear all interrupts in VIC. This resets the priority hardware.
}
/*-----------------------------------------------------------*/
